In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability realizes both nFET pFET electrical characteristics when adequately biased. The use of will significantly reduce the count in realizing sequential combinational circuits result highly compact design. uses dual fin structure having single mid-gap workfunction gate ( $\sim $ 4.65 eV) alongsid...

1. Abstract We have studied the statistical variability (SV) in thinbody silicon-on-insulator (TBSOI) MOSFETs with high-κ/metal gate stacks. We have considered the impact of the gate workfunction variation (WFV) in conjunction with random discrete dopants (RDD) and trapped interface charges. The simulations were carried with the Glasgow 3D ’atomistic’ simulator GARAND. Results for both threshol...

Results are presented on the performance of a heterojunction interfacial workfunction internal photoemission ~HEIWIP! wavelength-tailorable detector. The detection mechanism is based on free-carrier absorption in the heavily doped emitter regions and internal emission across a workfunction barrier caused by the band gap offset at the heterojunction. The HEIWIP detectors have the high responsivi...

Metal-insulator-semiconductor (MIS) photoelectrodes offer a simple alternative to the traditional semiconductor-liquid junction and the conventional p-n junction electrode. Highly efficient MIS photoanodes require interfacial surface passivating oxides and high workfunction metals to produce a high photovoltage. Herein, we investigate and analyze the effect of interfacial oxides and metal workf...

MOSFET scaling and performance has progressed rapidly in recent years, with physical gate lengths for electrostatically sound devices reaching 30 nm or below: near the prospective scaling limits for traditional bulk MOSFETs. This work investigates several key issues for this "end of roadmap" regime. Focus is on understanding the limitations to carrier velocity in MOSFET inversion layers as chan...

When a low-energy electron is incident on an interface between a metal and superconductor, it causes the injection of a Cooper pair into the superconductor and the generation of a hole that reflects back into the metal—a process known as Andreev reflection. In confined geometries, this process can give rise to discrete Andreev bound states (ABS), which can enable transport of supercurrents thro...

Low-resistance printed conductors are crucial for the development of ultra-low cost electronic systems such as radio frequency identification tags. Low resistance conductors are required to enable the fabrication of high-Q inductors, capacitors, tuned circuits, and interconnects. Furthermore, conductors of appropriate workfunction are also required to enable fabrication of printed Schottky diod...

Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes...

Based on the parabolic potential approach (PPA), scaling theory, and driftdiffusion approach (DDA) with effective band gap widening (BGW), we propose an analytical subthreshold current/swing model for junctionless (JL) cylindrical nanowire FETs (JLCNFETs). The work indicates that the electron density of Qm that is induced by the current factor minimum central potentialc,minand equivalen...

Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ ( > 20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5-0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration ...