| We have developed an architectureoriented routing method for a telecommunications FPGA(Field-Programmable Gate Array) which has rich hierarchical routing resources. Our routing method consists of four routing procedures, each of which are related to a speci c part of the routing resource architecture of the FPGA. It can accomplish routing results almost ve times faster than a reference method...

In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan fami...

To date, some types of Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize capabilities of rapid reconfiguration with numerous reconfiguration contexts. However, the layout style requires a shield against the reconfiguration light irradiation to guard transistors that constitute the gate array. This paper presents a shield effect for a circuit that is implemented on a ga...

Achim G. Ho mann University of New South Wales School of Cumputer Science and Engineering P.O. Box 1, Kensington, Sydney, NSW 2033, Australia Abstract A new strategy for layout synthesis is presented. The GGADS system which uses the strategy has been implemented and is capable of designing layouts for congurable gate array master structures. GGADS evaluates the e ectiveness of layouts on gate a...

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arr...

High-speed reconfigurable processors incorporating a reconfigurable memory and microprocessor array into a chip have been developed [1]. Such devices use a context-switching method. Their internal reconfigurable memory includes reconfiguration contexts of 16 banks. One bank includes a reconfiguration context used for ALUs that can be changed to others on a clock in nanoseconds. These devices ha...

In this paper, the design and implementation of a real-time traffic light control system based on Fieldprogrammable Gate Array (FPGA) technology is reported. The traffic light control system is designed with VHDL language. Its function was verified with simulation. After that, the VHDL design was downloaded to FPGA board hardware to verify its function in experiment. The designed traffic light ...

We show how, given any set of generators of the stabilizer of a quantum code, an eecient gate array that computes the codewords can be constructed. For an n-qubit code whose stabilizer has d generators, the resulting gate array consists of O(nd) operations, and converts k-qubit data (where k = n ? d) into n-qubit codewords.

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-...