In this paper the experimental equipment for UV-programming of floating-gate circuits are presented along with initial results on concurrent UV-programming of digital floating-gate circuits. It is demonstrated that concurrent UV-programming is possible when using real-time reconfigurable gates (Universal Gates). It is also shown that openings in the passivation, enabling UV-programming, works t...

A flexible analog pattern-matching classifier has been developed and its performance is demonstrated in conjunction with a robust image representation algorithm called projected principal-edge distribution (PPED). In the circuit, the functional form of matching is made tunable in terms of the peak position, the peak height and the sharpness of the similarity evaluation by employing the floating...

We investigated the recharging process of commercial floating gate device (EPAD) during six different dose rates and ten irradiation cycles with highest rate. Dose rate dependence dosimeter was observed from 1 Gy/h to 26 ( H 2 O ). There is no change dosimetric characteristic a constant for cycles. The absorbed does not affect drift threshold voltage readings after steps. reprogramming degradin...

The floating gate technique (FGT) is a very sensitive method to measure very low level leakage currents in MOS capacitors. This indirect technique requires the precise knowledge of the capacitance of the structure under test. We have studied the impact of the capacitance model (classic or quantum) and of polysilicon gate depletion effect. We have shown that for 7.2 nm thin EEPROM tunnel oxides,...

This paper introduces the Field-Programmable Learning Array, a new paradigm for rapid prototyping of learning primitives and machinelearning algorithms in silicon. The FPLA is a mixed-signal counterpart to the all-digital Field-Programmable Gate Array in that it enables rapid prototyping of algorithms in hardware. Unlike the FPGA, the FPLA is targeted directly for machine learning by providing ...

Absbact-A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It featum complete reset that results in no kTC noise and no image lag, hlgh blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 3 2 0 x 2 7...

Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use o...

A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and railto-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hotelectron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feed...