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The paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system.

In this paper, we address the main aspects of partial reconfiguration on the Xilinx Virtex FPGAs and explain how to overcome main challenges during partial reconfiguration design and implementation, in specific about signal integrity, global logic and inter-module communication. In addition, we discuss the problem of designing partial reconfigurable application using the HandelC language, and i...

Redundancy is a critical component to the design of fault tolerant systems; both hardware and software. This paper explores the possibilities of using evolutionary techniques to first produce a processing system that will perform a required function, and then consider its applicability for producing useful redundancy that can be made use of in the presence of faults, ie is it fault tolerant? Re...

In this paper we present a novel RAM-based field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog ...

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in progr...

The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable Gate Arrays (FPGAs) are described. These BIST configurations completely test the programmable logic and routing resources in the core of the FPGA along with the dedicated Random Access Memories (RAMs) dispersed within the array. The BIST configurations are generated usi...

Reconfigurable hardware is a potential technique, which improves the performance of the systems being implemented in it. In this paper, the implementation of an ECG system for detection of abnormalities in real time has been considered using the Partial Reconfiguration technique. The implementation has been done in the Virtex-5 FPGA hardware using Verilog HDL. The performance of the implemented...

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