Fault tolerant circuits are currently required in several major application sectors. Besides and in complement to other possible approaches such as proving or analytical modeling whose applicability and accuracy are significantly restricted in the case of complex fault tolerant systems, fault-injection has been recognized to be particularly attractive and valuable. Fault injection provides a me...

A general design technique for achieving single faulttolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieve...

Physical implementations of cryptographic algorithms leak information, which makes them vulnerable to so-called side-channel attacks. The problem of secure computation in the presence of leakage is generally known as leakage resilience. In this work, we establish a connection between leakage resilience and fault-tolerant quantum computation. We first prove that for a general leakage model, ther...

This paper addresses the soft-error problem in UDSM circuits by presenting on-line fault-tolerant circuit design techniques. In our scheme, separate dual transistor (SDT) structure is introduced into the register design as a key component to increase the input-signal stability as well as the robustness of the circuit against the effects of ionizing particles. Our work not only demonstrates the ...

Determining the optimal implementation of a quantum gate is critical for designing a quantum computer. We consider the crucial task of efficiently decomposing a general single-qubit quantum gate into a sequence of fault-tolerant quantum operations. For a given single-qubit circuit, we construct an optimal gate sequence consisting of fault-tolerant Hadamard (H) and π/8 rotations (T ). Our scheme...

The values of electronic components are always deviated, but the functions of the modern circuits are more and more precise, which makes the automatic fault diagnosis of analog circuits very complex and difficult. This paper presents an extension-neural-network-type-1ENN-1based method for fault diagnosis of analog circuits. This proposed method combines the extension theory and neural networks ...

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause...

This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and te...

In this paper, we study the problem of constructing a sorting circuit, network, or PRAM algorithm that is tolerant to faults. For the most part, we focus on fault patterns that are random, i.e., where the result of each comparison is independently faulty with probability upper-bounded by some constant. All previous fault-tolerant sorting circuits, networks, and parallel algorithms require (log ...