Fast multiplication can be constructed by combining the tree structure of multiplication's addition, i.e. Wallace tree, with the parallel on-they conversion to have a multiplication without using any carry propagation adder at the end. This parallel on-they conversion speeds up the conversion of redundant binary to conventional binary. With the delay of n 4 , we can have the conversion from red...

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consump...

This paper presents a fast, low-power, binary carrylookahead, 64-bit dynamic parallel adder architecture for highfrequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by selfresetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation...

Abstract—Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits which are designed to perform high-speed arithmetic operations. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was modified by Neelam Sharma in 2006 using universal logic. The proposed adder is re-modified for reducing the number of gates and thus the circuit complexity and cost. Further due to...

Parallel-prefix adders (also known as carry tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and...

In this paper an extensive study on several adders has been manifested to design VLSI applications. Adder circuits plays a major role to modify or design a multiplier. Imprecise adder is one of the design where used in increasing the performance and power efficiency and approximate adders are for error detection and correction.16T full adders is also used to fast and energy efficient adder. An ...

DFT and FFTs are important but resource intensive building blocks and have found many application in communication systems ranging from fast convolution to coding of OFDM signals. It has recently be shown that the n-Dimensional Reduced Adder Graph (RAG-n) technique is beneficially in many applications such as FIR or IIR filters, where multiplier can be grouped in multiplier blocks. This paper e...

-The saying goes that if you can count, you can control. Addition is a fundamental operation for any digital system, digital signal processing or a control system. A fast and accurate operation of a digital system is greatly influenced by the performance of resident adders. In this regard, an efficient hybrid adder that combines a carry select adder and a ripple carry adder using QCA technology...

Many Digital Signal Processing (DSP) algorithms use floating-point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal of every VLSI designer. This paper presents a comparison of pipelined floating-point adder complaint with IEEE 754 format with an unpipelined adder also compl...

Nuno Roma and Tiago Dias and Leonel Sousa Dept. of Electrical and Computer Engineering, I.S.T. / INESC-ID R. Alves Redol, 9, 1000-029 Lisboa, Portugal Email: [email protected], [email protected], [email protected] Abstract— This paper presents a detailed comparison analysis of several fast adder architectures for high performance VLSI design. The evaluation of those architectures is firs...