The substrate-triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits for the input, output, and power pins have been designed and verified in a 0.18m salicid...

A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for highfrequency applications. The device dimension ...

The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more...

Acceptance control charts are effective tools tomonitor capable processes in which the fraction of the produced nonconforming items is very low. In these charts, some controlled changes in the process mean are allowed, and the production of a specified number of defectives is tolerated. Designing these acceptance control charts by considering the cost of sampling, detecting, and investigating o...

Finalement, je tiensà remercier ma famille et mes amis pour leur soutien et, tout simple-ment, pour leur présencè a mes côtés en toutes circonstances.

Abstract On-chip electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the na...

INTRODUCTION The elevated risk of complications and technical complexity of endoscopic submucosal dissection (ESD) has limited its implementation in our medical system. OBJECTIVE To design and evaluate a training program for learning the ESD technique. METHODS Four endoscopists with no experience with ESD underwent a 4-step training program: 1) review of the existing literature, didactic ma...

This report presents a comprehensive investigation on the advantages of using copper interconnects in ESD protection designs. 4KV GGMOS ESD protection structures using Cu interconnects, a 2GHz ring oscillator circuit and a low-power, high-speed Op Amp circuit were designed for comparison study. In Phase I, simulation results show that, while ESD protection devices may inevitably affect circuit ...

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage ( 7.5 V), short response time (0.18–0.4 ns), symmetric deep-snapback – characteristics, and low on-resistance ( ). It passed the 14-kV human b...

−Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed. Index Terms−Reli...