A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (nVDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length Lg. A tremendous improvement in the drive-on current is noted. The electron concentration profil...

Abstract Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with silicon channel utilizing sectorial cross section is evaluated in terms Ion/Ioff current ratio, transconductance, subthreshold slope, threshold voltage roll-off, drain induced barrier lowering (DIBL). In addition, the scaling behavior electronic figures merit comprehensively studi...

A comprehensive study of the scaling negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm comes two nodes after industry "3nm node," which has 16nm Lg last node according International Roadmap for Devices Systems (IRDS). In addition, intervening nodes, meet IRDS Ion Ioff target at target-beating VDD. The benefits ...

This research paper explains the effect of dimensions Gate-all-around Si nanowire tunneling field transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors characteristics tunnel transistors. The Silvaco TCAD has been used to study electrical TFET. Output (gate voltage-d...

We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature 77 K-300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage ( $V_{\mathrm{ th...

In this paper we study the feasibility of design/fabrication a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints depth P+ implantation. The doping profile is obtained using Monte Carlo implantation simulation. calculation used drift-diffusion approach. JFET aims to achieve threshold voltage of-3V. We found that constraint in concomitance with propose...

We developed a double-recess etching process and a new Digital-Oxide-Deposition (DOD) technique to fabricate 180nm low-threshold GaN Metal-OxideSemiconductor Double Heterostructure Field Effect Transistors (MOS-DHFET). Two device layer structures, InGaN channel design and InGaN back-barrier design, were employed to improve the confinement of TwoDimensional Electron Gas (2DEG) and mitigate the s...

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation channel field formation. Further, internal gate's threshold voltage ( V TH1 ) could be reduced compared external TH2 by arranging work-function Double devices. Therefore, device CSDG realized instigat...

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K varied side-gate biasing ( ${V}_{\text {side}}$ ). The subthreshold slope (S...

Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field will further generat...