In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A ...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

Yong-Bin Kim* Tom Chen** *Microelectronics Division Samsung Electronics Co. San Jose, CA, USA **Department of Electrical Engineering Colorado State Univ. Fort Collins, CO 80523, USA Abstract This paper describes a CMOS variable delay line Delay Locked Loop(DLL) circuit speci cally designed for reducing clock skew on DRAM/Logic merged integrated circuit using 0.6 m CMOS process. A phase detector...

Location estimation in Wireless networks has become an important feature for improvement in public safety service. Its potential applications include location sensitive billing, asset tracking, fraud protection, mobile yellow pages, fleet management, etc. Several location techniques using terrestrial wireless network elements and radio signals have been proposed over the years, but multipath pr...

The paper presents “A CMOS Delay Lock Loop with Dual Control”. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A preci...

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary cha...

The performance of a coherent delay-locked tracking scheme for direct-sequence/spread-spectrum systems using half-sine or triangular chip waveforms for early and late despreading sequences is analyzed. The effect of band-limiting on the received signals is considered. Mean time to lose lock (MTLL) and root mean square (rms) tracking error of the delay-locked loop (DLL) are compared with that of...

—For positioning with Global Navigation Satellite System (GNSS) in urban canyon area, besides the weak signal power, the satellite signal may also be frequently sheltered and no power can be received. It is a great challenge for the GNSS receiver to keep positioning continuously. If the tracking loop in GNSS receivers can recover locking the signal soon after the signal appears again, it will ...

Abstract: This paper describes the architecture and performance of a high-resolution time–to– digital converter (TDC) based on a Vernier delay line. The TDC is used as a basic building block for time interval measurement in an ultrasonic liquid flowmeter. Operation of the TDC with 10ps LSB resolution and 1 ms input range has been simulated using library models for 1.2 μm double–metal double–pol...