Modern microelectronics and nanoelectronics devices rely on the drift of electron localized at the interfaces between different materials, such silicon and silicon dioxide or gallium arsenide and aluminum gallium arsenide. Hence, the electron drift transit time in the active region of a device determines the maximum device speed. Instead of the electron drift, we propose to use the waves of the...

Various compact models have been of great interest and studied for deep-submicron metal-oxide-semiconductor field effect transistor (MOSFET) device simulation. The model parameters extraction intrinsically characterizes properties of designed and fabricated devices. It leads to a multidimensional optimization problem to be solved and extracted efficiently for the applications to very large scal...

There is a demand for portable devices like mobiles and laptops etc. and their long battery life. For high integrity CMOS VLSI circuit design in deep submicron regime, feature size is reduced according to the improved technology. Reduced feature size devices need low power for their operation. Reduced power supply, reduces the threshold voltage of the device. Low threshold devices have improved...

With the scaling of feature sizes into Deep-Submicron (DSM) values, the level of integration and performance achievable in VLSI chips increases. A lot of work has been directed to tackle design related issues arising out of scaling, like leakage mitigation etc. However efforts to enhance testability of such designs have not been sufficient. It is not viable to overlook testability issues arisin...

The increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performance degradation and need to be addressed both in the design for deep submicron and testing for deep submicron phase. Existing delay testing tec...

A simple general-purpose I-V model for all operating modes of deep-submicron MOSFETs is presented. Considering the most dominant short channel effects with simple equations including few extra parameters, a reasonable trade-off between simplicity and accuracy is established. To further improve the accuracy, model parameters are optimized over various channel widths and full range of operating v...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

A-Tree is a rectilinear Steiner tree in which every sink is connected to a driver by a shortest length path, while simultaneously minimizing total wire length. This paper presents a polynomial approximation algorithm for the generalized version of A-Tree problem with upper-bounded delays along each path from the driver to the sinks and with restrictions on the number of Steiner nodes. We refer ...

Given the oft-cited difficulty of testing modern integrated circuits, the fact that CMOS ICs lend themselves to IDDQ testing is a piece of good fortune. But that valuable advantage is threatened by the rush of semiconductor technology to smaller feature sizes and faster, denser circuits, in line with the Semiconductor Industry Association's (SIA) Roadmap--its forecast for the CMOS IC industry. ...