This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are ...

This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which wi...

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. ...

Inevitably, reading is one of the requirements to be undergone. To improve the performance and quality, someone needs to have something new every day. It will suggest you to have more inspirations, then. However, the needs of inspirations will make you searching for some sources. Even from the other people experience, internet, and many books. Books and internet are the recommended media to hel...

Ultra Deep-Sub-Micron CMOS chips have to function correctly and reliably, not only during their early postfabrication life, but also for their entire life span. In this paper, we present an architectural-level in-field repair technique. The key idea is to trade area for reliability by adding repair features to the system while keeping the power and the performance overheads as low as possible. ...

In modern digital circuits the total power attributed to wires is increasing. Reducing the power consumption in wires play a major role in low power design. Coupling transitions contribute to significant energy loss in deep sub-micron buses. Earlier schemes using the switching activity minimization based upon the substrate capacitances are not valid in these buses. Hence, a new low energy bus-e...

In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the th...

A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an eficient plarforrn forfast and accurate static timing verijcution of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the ...