Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memo...

To meet the requirement of distributed video coding (DVC) in resource-limited sensor networks, Wyner-Ziv theorem-based source coding with side information only available at the decoder states that an intraframe encoder with interframe decoder system can achieve comparable coding efficiency of a conventional interframe encoder and interframe decoder system. In this paper, firstly, a block discre...

-This paper proposed a generic data packing scheme for quasi-cyclic LDPC codes decoder which has two advantages. Firstly, in this scheme no shift network is needed, it greatly reduces the area of the LDPC decoder. Secondly, in this scheme, all the messages in a row can be accessed from memories in one cycle, it increase the throughput of LDPC decoder. A LDPC decoder architecture using the data ...

The very powerful turbo codes are the most recent breakthrough in coding theory. The implementation of the iterative turbo decoder however hampers their incorporation in real systems. We tackle this problem by optimizing the decoder on two levels: the separate decoder modules and the global decoder system. Our module level optimizations greatly reduce the decoding delay and energy. The main con...

Quantum dot cellular Automata technology is used in this paper which overcomes the design constraints of nanoscale CMOS circuits. This paper presents the analysis of 2:4 decoder circuit using four different methodologies. QCA based Decoder circuit is implemented using coupled majority voter minority gate, 45 0 rotated cells, multilayer wire crossings and five input Majority Voter gate. Comparat...

This paper proposes an optimal joint source-channel, maximum a posteriori, decoder for entropy coded Markov sources transmitted over noisy channels. We introduce the concept of incomplete and complete states to deal with the problem of variable length source codes in the decoder. The proposed decoder is sequential, there by making the expected delay finite. When compared to the standard Huffman...

In 2004, a new standardization activity called reconfigurable video coding (RVC) was started by MPEG with the purpose of offering a framework which provides reconfiguration capabilities for standard video coding technology. The essential idea of RVC framework is a dynamic dataflow mechanism of constructing new video codecs by a collection of video coding tools from video tool libraries. With th...

\Ve present. an approach for df'velopment of a decoder for any complex binary error-correct.ing code(ECC) via training from examples of decoded received words. Our decoder is a connectionist architecture. We describe two sepa.rate solutions: A system-level solution (the Cascaded Networks Decoder); and the ECC-Enhanced Decoder, a solution which simplifies the mapping problem which must be solved...

In this paper, Reed Solomon (RS) decoder adopting the pipelined reduced inversion free Berlekamp Massey (pRiBM) algorithm is proposed. This Reed Solomon decoder is designed by equipping the Syndrome Computation unit, Key Equation Solver (KES), Chien search and Forney algorithm unit. The RS decoder requires long latency for decoding large number of test vectors. Therefore, the Reed Solomon decod...