In this paper, PLL are most frequently used for Local Oscillator (LO) signal generation in wireless radio transceivers to down convert the carrier frequency to lower or intermediate frequency . The input reference frequency is 6.4 MHz. The architecture used for the design of Frequency synthesizer was Integer-N architecture. This was designed using 0.25 μm technology. The VCO designed was a CMOS...

Combination of A/D-D/A converters allows implementing both long-term analog memory and multiplier/divider operations. An efficient design based on continuous-time, current-mode, dividing-algorithmic converters is presented in this paper. It offers high-speed and low-voltage operation with low or middle resolution. Experimental results of two CMOS-2.4μm prototypes (with 5and 7-bit data converter...

A four-way power divider/power combiner using substrate integrated waveguide (SIW) and microstrip lines is proposed and investigated. The proposed power divider consists of a double-layer substrate with a bottom layer including an SIW T-junction and a top layer including a microstrip network. This microstrip network consists of a modified Gysel power divider which provides a high isolation betw...

This article presents a new current-mode multiplier/divider based on MO-CDTA (Multiple output current conveyor transconductance amplifier). The circuit description is very simple, its construction consists of only one MO-CDTA. Without external passive elements, the proposed circuit is then suitable for IC architecture. The PSpice simulation and experimental results are depicted, and agree well ...

A high-speed low power scalable programmable dual modulus digital CMOS frequency divider architecture is proposed. The unique frequency divider architecture includes a high speed parallel counter with State Excitation Module, a switchover trigger circuit, a modulus switchover circuit and a reloader circuit. The mode switchover circuit has two sets of external programmable inputs for two alterna...

An ultra-wideband unequal-split Wilkinson power divider with a 2:1 split ratio is presented. To achieve the ultra-wideband characteristics, the conventional quarter-wave arms of the divider are replaced by tapered lines. Moreover, two extra tapered transformers are incorporated at the output ports for matching purposes as the designed divider is of an unequal-split type. To obtain good isolatio...

This work presents the fastest Current Mode Logic static frequency divider to date. The circuit is fabricated in a commercially available InP process. Microwave techniques are used to achieve speeds of 75 GHz without resort to emitter followers. Interconnect design is stressed and the results of several variations are presented. Microstrip, inverted microstrip, peaking inductors and keep-alive ...