Crossbar-based switches are commonly used to implement routers with throughputs up to about 1 Tb/s. The advent of work-conserving crossbar scheduling algorithms now makes it possible to engineer systems that perform well, even under extreme traffic conditions. Unfortunately, all the published work-conservation results for crossbar scheduling apply only to systems that switch fixed-length cells,...

Molecular electronics offer an alternative pathway to construct nanoscale circuits in which the critical dimension is naturally associated with molecular sizes. We describe the fabrication and testing of nanoscale molecular-electronic circuits that comprise a molecular monolayer of [2]rotaxanes sandwiched between metal nanowires to form an 8 × 8 crossbar within a 1 μm2 area. The resistance at e...

In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting...

We propose a novel architecture, a Combined Input-CrosspointOutput Buffered (CIXOB-k, where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100% throughput under uniform and unbalanced traffic. It also provides timing relaxation and scalability. CIXOB-k is based on a switch with Combined Input-Crosspoint Buffering (CIXB-k) and round-robin arbitration. CIXB-k has a ...

∗— Output-Queued (OQ) switching architecture is known to be of optimal performance amongst all queuing approaches. However, OQ switches were always known to lack scalability due to the high memory bandwidth constraints. Extensive research work showed that an OQ switch can be exactly emulated by a more scalable crossbar switch (i.e., InputQueued (IQ) switch) and a small speedup[9]. Unfortunately...

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar with two multiplexers. The presented simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, studied optimized terms cell number, occupied area, number clocks, energy consumption. Using provided switch, bas...

Over the years, different architectures have been investigated for the design and implementation of high-performance switches. Particular architectures were determined by a number of factors based on performance, flexibility and available technology. Design differences were mainly a variation in the queuing functions and the switch core. The crossbar-based architecture is perhaps the dominant a...

We describe the implementation of a 128×128 crossbar switch in 90nm CMOS standard-cell ASIC technology. The crossbar operates at 750MHz and is 32-bits wide to provide a port capacity above 20Gb/s, while fitting in a silicon area as small as 6.6mm by filling it at the 90% level (control not included). Next, we arrange 128 1mm “user tiles” around the crossbar, forming a 150mm die, and we connect ...

The nanowire crossbar is a promising nanotechnology for assembling memories and circuits. In both, a small number of lithographically produced mesoscale wires (MWs) must control a large number of nanoscale wires (NWs). Previous strategies for achieving this have been vunerable to misalignment. In this paper, we introduce core-shell NWs, which eliminate misalignment errors. We also give a two-st...