We designed and implemented an ultra low power CORDIC processor which targets the implementation We propose a modified CORDIC algorithm and architecture. and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes. in rotate mode, on average 50 Jl, W @ 10 MHz under 1 V supply voltage in a .25 Jl,m technology.

In this paper we analyze an architectural extension for a Sandbridge processor which encompasses a CORDIC functional unit and the associated instructions. Specifically, the first instruction is CFG CORDIC that configure the CORDIC unit in one of the rotation and vectoring modes for circular, linear, and hyperbolic coordinate systems. The second instruction is RUN CORDIC that launches CORDIC ope...

This paper is focused on the implementation of CO-ordinate Rotation Digital Ccomputer (CORDIC) algorithm in wireless Local Area Network (WLAN) receiver. The primary task is to create a VHDL description for CORDIC vector rotation algorithm. The basic work has been carried out in MATLAB. The VHDL implementation of the CORDIC algorithm is based on the results obtained from the MATLAB’s simulation ...

This paper describes a modification to the three dimensional CORDIC algorithm using an approximation of the Taylor series. The modification has the potential to reduce the number of iterations required for a three dimensional CORDIC operation by at least 25%. The approach used is based upon a modification of the two dimensional CORDIC algorithm originally suggested by H.M Ahmed[1]. Introduction...

CORDIC based IIR digital lters possess desirable properties for VLSI implementations such as regularity, local connection, low sensitivity to nite word-length implementation, and elimination of limit cycles. Recently, ne-grain pipelined CORDIC based IIR digital lter architectures which can perform the ltering operations at arbitrarily high sample rates at the cost of linear increase in hardware...

CORDIC based IIR digital lters are orthogonal lters whose internal computations consist of orthogonal transformations. These lters possess desirable properties for VLSI implementations such as regularity, local connection, low sensitivity to nite word-length implementation, and elimination of limit cycles. Recently, ne-grain pipelined CORDIC based IIR digital lter architectures which can perfor...

COordinate Rotation DIgital Computer (CORDIC) algorithm has potential for efficient and low-cost implementation of a large class of applications which include the generation of trigonometric, logarithmic and transcendental elementary functions, complex number multiplication, matrix inversion, solution of linear systems and general scientific computation. This paper presents a brief overview of ...

In spite of several modified versions proposed, there is a huge demand for an efficient implementation of CORDIC in signal processing applications. Various methods proposed for CORDIC have their own drawbacks either in range of functionality or complexity. This paper presents speed optimized scale-free CORDIC in order to be mainly used in signal processing applications such as FFT and DCT etc.T...

Different architectures have been proposed for FPGA implementation of Universal Modulator. The Look up table (LUT) technique is one way of realizing universal modulator. Here the CORDIC is used for efficient realization of Universal Modulator. The coordinate rotation digital computer (CORDIC) algorithm is widely used in various technological fields such as digital signal processing (DSP), biome...

In this work, a fast radix-4 redundant CORDIC algorithm with variable scale factor is proposed. The algorithm includes an on-line scale factor decomposition algorithm that transforms the complicated variable scale factor into a sequence of simple shift-and-add operations and does the variable scale factor compensation in the same fashion. On the other hand, the on-line decomposition algorithm i...