In this paper a new design of comparator is described with the help of Full adder which are the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper comparator are developed using various design of full ...

This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency; using Tanner EDA tool version 12.6 at ...

Dynamic comparators are popular structures used in analog circuits such as RFID tags, ADC, memory modules, etc. Compared with traditional open-loop amplifiers that can be used as a comparator, well-designed dynamic comparators are usually faster and more powerefficient, but dynamic CMPs also have some problems. Device mismatch-induced offset voltages is a major challenge when designing dynamic ...

I compare Frith and colleagues' influential comparator account of how the sense of agency is elicited to the multifactorial weighting model advocated by Synofzik and colleagues. I defend the comparator model from the common objection that the actual sensory consequences of action are not needed to elicit the sense of agency. I examine the comparator model's ability to explain the performance of...

An optimized room temperature resistance bridge (AccuBridgeTM), modeled after the cryogenic current comparator, has been developed to determine current ratio’s with the highest accuracy. The direct current comparator has been optimized to reduce the leakage effects of the comparator. In addition, new self calibrating direct current sources have been fabricated and tested. AccuBridgeTM relies on...

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Double-tail comparator is basically designed for SAR-ADC in order to optimize the power with which the circuit operates on high-speed. The circuit is designed under 90 nm CMOS technology means by reducing the technology the parameters get also redu...

The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC)...