Scan paths an: generally added to a sequential cileuit in a final design for testability step. We present an approach to incorporate the behavior of a scan path during circuit synthesis. thus avoiding to implement the scan path shift register as a separate structural entity. The shift transitions of the scan path an: trcalCd as a pan of the system functionality. Depending on the minimization st...

To conquer the scalability issue of evolvable hardware, this paper proposes a multi-virtual reconfigurable circuit (VRC) cores-based evolvable system to evolve combinational logic circuits in parallel. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several subcircuits, and each of them is evolved independently as a subcomponent by its corresponding VRC...

ABSTRACT This paper presents a combinational system, which can perform the functionalities of Auto Focus (AF) and Auto Exposure (AE) at the same time in a very efficient manner. At the first step, this system uses a DOG (Difference of Gaussian) filter to measure image’s contrast and sharpness simultaneously. Then, a fuzzy logic-based scheme is proposed for the adjustment of focus and exposure. ...

Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increasingly important in combinational logic circuits. Combinational logic is resilient to soft errors due to three masking phenomena: (1) Logical Masking, (2) Electrical Masking, and (3) Latching-window Masking. This paper concentrates on logical masking, and proposes a probabilistic model which calcu...

Since the NULL Convention Logic (NCL) paradigm is delay-insensitive, NCL combinational circuits cannot be partitioned indiscriminately when pipelining, as can clocked circuits. Instead, these circuits must be partitioned into stages, such that each stage is inputcomplete with respect to all of its inputs and delayinsensitivity is maintained. Therefore the selected architecture for an NCL circui...

With the increase of complexity of circuits, guaranteeing the correctness of design becomes extremely important. A new equivalence checking method is presented in this paper for the verifications of combinational circuits; the method uses the chaotic pattern simulation to find a lot of equivalent nodes, which results in that the scale of the composite circuit is reduced. The equivalence checkin...