Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanc...

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been pro...

This paper presents a comprehensive survey of existing techniques for interconnect optimizationduring the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various d...

In this paper, we investigate the effect of multilevel networks on clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effects of shunt segments contributed by the mesh is derived analytically from the simplified model. The result indicates that the skew decreases proportionally to the exponential of −Rs/R, where Rs is the drivin...

Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing ...

In this paper, we present an automatic clock tree design (ACTD) system for high speed VLSI designs. The ACTD is designed to extend the capabilities of the existing computer aided design tools and provides a convenient environment to CAD users. We have developed new theoretical analyses and heuristics. Specifically, the following issues are considered: (i) a planar clock routing, (ii) a solution...

To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO r...

Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A methodology for enhancing the layout of the clock tree to reduce the uncertainty of the clock signal is presented in this paper. The primary objective of the proposed methodology ...