This paper addresses the challenge of building an automated decision support methodology to tackle the complex problem faced every day by runway controllers at London Heathrow Airport. Aircraft taxi from stands to holding areas at the end of the current take-off runway where they wait in queues for permission to take off. A runway controller attempts to find the best order for aircraft to take ...

DEMIRCIOGLU, HARUN. Modeling Layout Dependent Stress Effects for CMOS. (Under the direction of Dr. W. Rhett Davis.) Process induced mechanical stress has enabled continued CMOS scaling since the 90nm node to improve carrier transport and maintain high drive current. This stress depends strongly on the layout shape as well as the surroundings of each transistor in a circuit. The resulting stress...

Quality of a layout has the most direct impact in the manufacturability of a design. Traditionally, layout quality is ensured in the first order by design rules, i.e. if a layout is free of design rules violation, it is a good layout. It is assumed such a layout will be fabricated to specification. Moreover, a design rule clean layout also ensures the electrical performance of the circuit it re...

This paper investigates how individual perceptions and attitudes about an organization influence multitasking behaviors in the workplace. While we know that individuals’ behaviors are influenced by the characteristics of their organizations (e.g., ICTs, physical layout), we still do not know much about how the way individuals interpret their organization influences their multitasking behaviors....

A perpendicular array PA,(t, k, u) is a n(y) by k array A of u distinct symbols, which satisfies: (i) every row of A contains k distinct symbols, (ii) for any t columns, and for any t distinct symbols, there are precisely 2 rows with the given symbols in the given columns. Such a structure may also be described as a A-uniform, t-homogeneous set of injective mappings from a k-set into a u-set. A...

The typical description of a VLSI layout is the geometrical description of masks. Layout verification [4] is the testing of a layout to see if it satisfies design and layout rules. An important problem in layout verification is layout device extraction, which involves detection of capacitors, resistors, transistors etc. from the geometrical description of masks. The layout extraction process st...

Modern integrated circuits (IC) operate in environment of various destabilizing factors which have essential influence on the operation of these circuits and often even disturb the normal operation. One of these destabilizing factors is the cosmic radiation, particularly total ionization dose effects (TID). For modern TID tolerant ICs [1-4] design is being done by circuit designers. In this pap...

An efficient approach to optimize the performance of integrated analog circuits is described. The main objectives are to speed up the design process and obtain better, possibly optimal, performance compared to manual simulation-based device sizing schemes. The automatic generation of the cost function requires only a circuit netlist, a performance specification, and process parameters supplied ...

As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The purpose of this paper is to present the layout design of...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...