This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [6,7]. The multiplier operates least significant bit (LSB)-first....

This paper presents an extra regular, Two recently proposed designs, as the typical complexity-reduced, high-performance pipelined examples of the improved conventional architectures, multiplier architecture, using newly proposed multiplier are rectangular-styled wallace tree multiplier (RSWM triple-expansion schemes. It is based on a parallel for short)) [2] and limited switch dynamic logic co...

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. The array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requisite of the modern ...

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of p...

ÐThe Massey-Omura multiplier of GF …2m† uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architecture o...

A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes it more efficient for VLSI implementation. Furthermore, a judicious deployment of larches in the circuit ensures that the multiplier operates on two coefficients of the multiplicand at the same time...

AbscrocrWe present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 x 128 vector-matrix multiplier on a single 3 mm x 3 mm ch...

New bit-parallel dual basis multipliers using the modified Booth s algorithm are presented. Due to the advantage of the modified Booth s algorithm, two bits are processed in parallel for reduction of both space and time complexities. A multiplexer-based structure has been proposed for realization of the proposed multiplication algorithm. We have shown that our multiplier saves about 9% space co...

This contribution describes a new class of arithmetic architectures for Galois fields GF (2k). The main applications of the architecture are public-key systems which are based on the discrete logarithm problem for elliptic curves. The architectures use a representation of the field GF (2k) as GF ((2n)m), where k = n · m. The approach explores bit parallel arithmetic in the subfield GF (2n), and...