In this paper, we introduce $(p,q)g-$Bessel multipliers in Banach spaces and we show that under some conditions a $(p,q)g-$Bessel multiplier is invertible. Also, we show the continuous dependency of $(p,q)g-$Bessel multipliers on their parameters.

‎in this paper‎, ‎we prove the nonexistence of two weighing matrices of‎ ‎weight 81‎, ‎namely $cw(88,81)$ and $cw(99,81)$‎. ‎we will apply two‎ ‎very different methods to do so; for the case of $cw(88,81)$‎, ‎we‎  ‎will use almost purely counting methods‎, ‎while for $cw(99,81)$‎, ‎we‎ ‎will use algebraic methods‎.

Multiplier is one of the essential element for all digital systems such as digital signal processors, microprocessors etc. In this paper, a new high speed multiplier using booth recoding technique is presented. This algorithm can be implemented by using the radix-8 booth recoding process. The proposed multiplier reduces the partial product array by almost 3/4 th the size of the bits. This reduc...

In this paper, IIR polyphase filters present several interesting properties: they require a very small number of multipliers to implement, they are inherently stable and have low round off noise sensitivity and no limit cycles. Furthermore, it is possible to achieve almost linear phase designs. Pulse shaping filters have been designed and implemented by using Raised cosine filter, Nyquist filte...

in this paper we introduce continuous $g$-bessel multipliers in hilbert spaces and investigate some of their properties. we provide some conditions under which a continuous $g$-bessel multiplier is a compact operator. also, we show the continuous dependency of continuous $g$-bessel multipliers on their parameters.

This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the sta...

This paper is published in: H. Fan, Researches in GF(2) Multiplication Algorithms, PhD dissertation, Tsinghua University, 2004. (in Chinese) Abstract A new GF(2) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the first multiplier is lower than a recently proposed nor...

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signiicantly reduced by a technique known as truncated multiplication. With this technique, the least ...