Implementation of switching activity in the all-optical domain is an essential aspect modern high-speed and secured communication technology. Micro-ring Resonator (MRR) based can be used to implement active low tri-state buffer logic clocked D flip-flop. The paper describes micro-ring resonator structures. further effective 4-bit memory register using appropriate arrangement buffers flip-flops ...

A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [I], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The ad...

All-optical flip-flops are key components for photonic digital processing in next generation optical networks and optical computing. In most digital applications signals synchronization with an external reference clock is a basic feature. In this paper an entire set of all-optical clocked flip-flops, including SR, D, T, and JK types is proposed and demonstrated. Each configuration employs a sin...

The proposed two types of multi-valued D flip-flops are NMAX-TG D flip-flop and NMIN-TG D flip-flop A NMAX-TG D flip-flop and a NMIN D flip-flop are composed of the components such as NMAX D flip-flops, NMIN D flip-flops and T-gate circuits. In the simulations, sampling frequencies of NMAX-TG D flip-flop and NMIN-TG D flip-flop are measured around 500 kHz and 1 MHz, respectively. The PDP parame...

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μ...