this paper presents a new method to reduce consumption power in flash adc in 65nm cmos technology. this method indicates a considerable reduction in consumption power, by removing comparators memories. the simulations used a frequency of 1 ghz, resulting in decreased consumption power by approximately 90% for different processing corners. in addition, in this paper the proposed method was desig...

Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology ...

Give a transistor-level circuit schematic and sketch a stick diagram for a Problem 11 Assume a CMOS inverter designed in the ON 0.5u CMOS process drives. Complementary MOSFET (CMOS) technology is widely used today to form circuits in numerous The circuit diagram of the CMOS inverter is shown in figure (4). 2.2 Charging and Discharging in CMOS Inverter...... 16. 2.3 Energy Recovery 5.31 Circuit ...

An optical receiver using a CMOS-compatible avalanche photodetector (CMOS-APD) is demonstrated. The CMOS-APD is fabricated with 0.18 μm standard CMOS technology and the optical receiver is implemented by using the CMOS-APD and a transimpedance amplifier on a board. The optical receiver can detect 6.25-Gb/s data with the help of the series inductive peaking effect.

Implantable image sensors have several biomedical applications due to their miniature size, light weight, and low power consumption achieved through sub-micron standard CMOS (Complementary Metal Oxide Semiconductor) technologies. The main applications are in specific cell labeling, neural activity detection, and biomedical imaging. In this paper the recent research studies on implantable CMOS i...

In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with g...