This paper provides a critical analysis of Objective VHDL, an object-oriented extension to VHDL. It is demonstrated that several design decisions lead to unnecessary complexity in the language and consequent modelling difficulty for designers. The SUAVE object-oriented extensions to VHDL, on the other hand, avoid these problems by more careful selection of language features.

There are problems in incorporating VHDL into the undergraduate curriculum in beginning computer architecture courses. The problems relate mainly to cost arising from two factors: VHDL tool availability and proper lecture material to coincide with the course objective(s). At the Georgia Institute of Technology, pilot VHDL lecture materials have been developed to address these two issues.

We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assignment statements. We present a VHDL interpreter in the form of rules of a concurrent evolving algebra which faithfully re ects and supports the view given in the VHDL'93 standard language reference manual.

One approach to accelerate a simulation of digital circuits described in VHDL is a distributed simulation of the VHDL model in a cluster of general purpose workstations. This paper describes an algorithm for the partitioning of the VHDL model, especially adapted for the requirements of this simulation type.

Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use within high integrity and safety critical systems. One commonly used coding language for their configuration is the VHSIC Hardware Description Language (VHDL). Whilst VHDL is used for hardware description, it is developed in a similar way to traditional software, and many safety critical software certification stan...

The VHDL domain replaces the VHDLF domain. It is not, however, meant to be used in the same way as the VHDLF domain: the VHDL domain is for generating code from functional block diagrams with SDF semantics, while the VHDLF domain was intended to contrast with the VHDLB domain. It supported structural code generation using VHDL blocks with no execution delay or timing behavior, just functionalit...

This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural ...

In Noctuids, storage proteins are taken up into fat body by receptor-mediated endocytosis. These include arylphorin and a second, structurally unrelated very high-density lipoprotein (VHDL). Previously, we have isolated a single storage protein receptor from the corn earworm, Helicoverpa zea, which binds both VHDL and arylphorin. The receptor protein is a basic, N-terminally blocked, approximat...

VHDL and other hardware description languages have become popular as system speci cation languages in top-down design. However, their constructs do not support the behavioral speci cation of embedded systems. We introduce a new conceptual design model, called Program-State Machines, that caters to embedded systems. We then describe the SpecCharts language, an extended version of VHDL, which sup...