The LNA is implemented using 90nm CMOS technology. The cascode topology with single-ended source degeneration using inductor is employed. The high gain is achieved by using common-source (CS) amplifier. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA. An inductance network (Lg, Ls) is used for input matching. An interstage ...

Abstract A differential Low-noise Amplifier (DLNA) using 0.13 μm CMOS technology is presented. The amplifier is optimized for Bluetooth Receiver applications operating in the 2.4 2.5 GHz band. The inductive degeneration topology used in the DLNA provides low noise, high gain and a large IIP3. The differential LNA was added a cascade output stage to the Single-ended source degenerated stage. Sim...

A broadband input matching technique for low noise amplifiers (LNAs) is presented which exploits an active feedback network to achieve better noise performance. The presented matching scheme is compared to the common-gate and conventional noise canceling structures. The noise performance of the presented technique is similar to that of the conventional noise canceling technique with much less p...

The capabilities of Horizontal Current Bipolar Transistor (HCBT) technology for radio frequency (RF) integrated circuit (IC) design is analyzed. The HBCT, with its novel technological approach and integration with existing CMOS technologies, is entering the testing phase on IC level. The demanding RF integrated circuit requirements and design issues in the frequency range 0.9 – 5 GHz are presen...

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-μ...

We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 μm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for the design of Differential Low Noise Amplifier. Consuming 9mA current a...

If you have a home-built receiver or transceiver for the amateur bands—or even manufactured equipment—that has proven weak in the front end, this article is for you. You could consider adding a band-pass filter at the input, which is desirable1 for second-order IMD protection; but it will not necessary help the third-order IMD, measured as third-order intercept point or IP3. That is the figure ...

A novel large input range source-follower based bi-quad filter cell is proposed offering an additional degree of freedom to the position of the poles and zeros. Simulation results of a 4th order fully differential elliptical filter in a 0.13μm CMOS technology confirm a power consumption of 160μA @ 1.2V, an IIP3 of 6.3 dBm and a steepness of 177 db/decade.