: In the microprocessors world SRAM play a vital role, but as the technology is scaling in nanometer, leakage current and leakage power both are the most known problems for SRAM cells in low power applications. More than 40% of the total power of the SRAM is waste due to the leakage through transistor. This paper compares the working, performance and results of two different SRAM topologies; a ...

ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the sta...

Scaling of gadgets in mass CMOS engineering helps short direct impacts and increment in spillage. Static arbitrary access memory (SRAM) is required to involve 90% of the zone of Soc. Since spillage turns into the essential variable in SRAM cell, it is actualized utilizing FinFet. FinFet gadgets got to be better option for profound submicron advances. In this paper, 6t SRAM cell is actualized ut...

This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data l...

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for ...

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much pr...

Embedded SRAMs can occupy the majority of the chip area in SoCs. The increased process spreads of modern scaled-down technologies and non-catastrophic defect-related sensitivity to environmental parameters can compromise the stability of SRAM cells, which is quantified by a low Static Noise Margin (SNM). A Stability Fault (SF) can present itself in a cell whose SNM is so small that it can accid...

This paper presents the analysis of dynamic noise margin of proposed 8T static random access memory (SRAM) cell. The proposed SRAM cell has two voltage sources, one connected to the bit line and the other is connected to bitbar line. These voltage sources are used to reduce the swing voltage at the output nodes. This reduction of swing voltage causes the reduction in dynamic power dissipation o...

The aim of paper is to get over the problem of 6T SRAM cell where it loses its reliability at low supplies due to degraded noise margins. These is done by using a 10T SRAM where the cell uses a charge sharing technique between the transistors so that SRAM could be made more rigid against the noises that can cause damage to the cell at low power supplies and along with that charge sharing betwee...

Leakage power is becoming the dominant power component in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM ...