Inactivation of cell death is a major step in tumor development, and p53, a tumor suppressor frequently mutated in cancer, is a critical mediator of cell death. While a role for p53 in apoptosis is well established, direct links to other pathways controlling cell death are unknown. Here we describe DRAM (damage-regulated autophagy modulator), a p53 target gene encoding a lysosomal protein that ...

DRAM is a lysosomal membrane protein and is critical for p53-mediated autophagy and apoptosis. DRAM has a potential tumor-suppressive function and is downregulated in many human cancers. However, the regulation of DRAM expression is poorly described so far. Here, we demonstrated that serum deprivation strongly induces DRAM expression in liver cancer cells and a core DNA sequence in the DRAM pro...

As the speed gap between processor and memory widens, data-intensive applications such as commercial workloads increase demands on main memory systems. Consequently, memory stall time—both latency time and bandwidth time—can increase dramatically, significantly impeding the performance of these applications. DRAM latency, or the minimum time for a DRAM to physically read or write data, mainly d...

......The main memory (dynamic RAM) system is a major limiter of computer system performance. In modern processors, which are overwhelmingly multicore (or multithreaded), the concurrently executing threads share the DRAM system, and different threads running on different cores can delay each other through resource contention. One thread’s memory requests can cause DRAM bank conflicts, row-buffe...

The memory wall is approaching: the time when increases in processor speed will be masked by the high penalty of misses to DRAM. It would seem that the time when we must regard DRAM as a slow peripheral is some way off. But, given the possibility that the inherent latency problem of DRAM may not be solved, that possibility needs to be addressed. This paper presents some thoughts on how future D...

Massive datasets prevalent in scale-out, enterprise, and high-performance computing are driving a trend toward ever-larger memory capacities per node. To satisfy the memory demands and maximize performance per unit cost, today’s commodity HPC and server nodes tend to feature multi-socket shared memory NUMA organizations. An important problem in these designs is the high latency of accessing mem...

This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower latency. This speed increase is achieved by not conserving the content of the DRAM cell after a read operation. Random access time to DRAM was reduced from 6 ns to 3 ns in a prototype made by Hwang et. al. A write-bac...

The RAMpage memory hierarchy addresses the growing concern about the memory wall – the possibility that the CPU-DRAM speed gap will ultimately limit the benefits of rapid improvement in CPU speed. Reducing references to DRAM is an increasingly desirable goal as CPU speed improves relative to DRAM. As the cost of a DRAM reference increases, it makes increasing sense to consider options like pinn...

DRAM is an important memory of a computer. Microprocessor loads the data requested by the user into DRAM before processing the data. Hence, DRAM contains important information in a computer. Recently, researchers discovered that DRAM is vulnerable to attack that is called Cold boot attack. DRAM contents can be recovered even after the computer has been powered off for several minutes. The infor...

Modern DRAM modules are often equipped with hardware error correction capabilities, especially for DRAM deployed in large-scale data centers, as process technology scaling has increased the susceptibility of these devices to errors. To provide fast error detection and correction, error-correcting codes (ECC) are placed on an additional DRAM chip in a DRAM module. This additional chip expands th...