Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digit...

Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based met...

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a convolutional network VLSI architecture using a hybrid approach composed of pulse-width modulation (PWM) and digit...

With the growth in complexity of VLSI circuits, test generation for sequential circuits is becoming increasingly diicult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more eeective and powerful sequential test generators. In this paper we describe and illustra...

Presents information on the 2022 VLSI Symposium.

With advancements in VLSI fabrication technology, interconnecting wires are being placed in closer proximity while circuits are starting to operate at higher frequencies. Thus, reduction in crosstalk between interconnects becomes an important consideration for VLSI physical design. In this paper, we have reviewed the effects and impact that crosstalk has on the performance and reliability of VL...