This paper discusses the programmable and dedicated approaches for real-time video processing applications. Various VLSI architecture including the design examples of both approaches are reviewed. Finally, discussions of several practical designs in video processing applications are then considered in VLSI architectures to provide significant guidelines to VLSI designers for any further real-ti...

This paper presents two architectures for 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first consists of transform module, RAM module and address sequencer. The transform module, which takes uniform and regular structure with local communication, offers many advantages, e.g. simple control flow, full hardware-utilization and low-power. The second architecture features parall...

Parallel VLSI Architectures for Multi-Gbps MIMO Communication Systems

This research presents for thejrst time an integer optimization approach for scheduling video computations on bus-constrained VLSI architectures or on an existing VLIWprocessor. For many video systems a combination of processor and VLSI chip provides a low cost solution that meets given performance requirements. Thus tools for analyzing whether a video function is best implemented in hardware (...

In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF × NF ) with O((NF )3) complexity to some FFT operations with O(NF log2(F )) complexity and the inverse of some (N × N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization a...

A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and per...

A data ow and control ow model is presented for use in high level synthesis of eecient time multiplexed architectures targeted towards real-time DSP systems. The model is an extension to the polyhedral models used in array synthesis techniques. The model features a mathematical description of dependencies between individual operations and signal instances of multi-dimensional signals for algori...