In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor fol...

The most common practice to model the transistor chain, as it appears in CMOS gates, is to collapse it to a single equivalent transistor. This method is analyzed and improvements are presented in this paper. Inherent shortcomings are removed and an effective transistor width is calculated taking into account the operating conditions of the structure, resulting in very good agreement with SPICE ...

A comprehensive modeling approach is applied to the study of pHEMT transistors for microwave power amplifier applications. This approach combines physical, electromagnetic and thermal simulations to model large power transistors used in these applications, allowing both the individual finger contribution and the global performance to be investigated in an efficient manner, which can be used wit...

In this paper, an analytical model for a vertical double implanted metal-oxide semiconductor (DIMOS) transistor structure in 4H-Silicon Carbide (SiC) is presented. Simulation for transport characteristics of the SiC MOSFET with the exact device geometry is carried out using the commercial device simulator MEDICI. A rigorous experimental testing and characterization is done on a 4H-SiC DIMOS tra...

In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model perfectly mat...

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the power dissi...

The corrections of the methodology of power BJT and MOSFET transistor models parameter extraction taking into account the self heating effects are presented For BJT these corrections are included into VBIC model parameter extraction process. For MOSFET current generator connected to standard SPICE MOS model is proposed to take into account drain current growth with transistor temperature.

Graphene based optical devices are highly recommended and interested for integrated optical circuits. As a main component of an optical link, a photodetector based on graphene nano-ribbons is proposed and studied. A quantum transport model is presented for simulation of a graphene nano-ribbon (GNR) -based photo-transistor based on non-equilibrium Green’s function method. In the proposed model a...

A new modeling method for DC-DC converter based on Cadence platform and Verilog-A is proposed in this paper. It provides a continuous-time model for system design, in which the transistor-level power stage, the compensation network and the error amplifier could be put together in, therefore provides accurate prediction of system loop transfer function frequency response. In addition, the proper...

A method for collapsing the transistor chain of CMOS gates to a single equivalent transistor is introduced. The width of the equivalent transistor is calculated taking into account the operating conditions of each transistor in the structure, resulting in very good agreement with SPICE simulations. Second order effects such as carrier velocity saturation in submicron devices, body effect and co...