Progress of integrated circuit technology allows integration of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise generated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-ba...

Analog and RF circuit performance in single-chip transceivers can severely suffer from coupling of digital switching noise to the silicon substrate. To predict this performance degradation, a deeper understanding of the impact of substrate noise is absolutely necessary. Using measurements, this impact is studied as the cascade of an attenuation through the substrate from the source of substrate...

Phase-locked loops (PLLs) are used in wireless receivers to implement a variety of functions, such as frequency synthesis, clock recovery, demodulation, and mixed-signal integrated circuits. Substrate coupling noise is a key problem in today’s large mixed-signal systems. Switching-noise generated by digital circuits can be coupled to sensitive analog circuits through the substrate, can degrade ...

While previous studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radio frequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolat...

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling ∆Σ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the ∆Σ modulator is studied....

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a freq...

Just as there are frictional losses associated with moving masses on a surface, what if there are frictional losses associated with moving information on a substrate? We propose to model these losses as proportional to “bit-meters,” i.e., the product of mass of information (i.e., its entropy) and the distance of information transport. For communication across a binary input AWGN channel, by obt...

| Substrate crosstalk modeling and analysis techniques for a reliable SoC oriented mixed signal IC design are outlined. Substrate noise measurements by use of a source follower and a latched comparator clearly indicate that L di=dt and R i e ects on Vdd/Gnd wirings appear in the substrate. An experimental full chip substrate crosstalk veri cation system based on a macroscopic substrate noise mo...

Introduction This work intends to develop new methodologies to evaluate efficiently and early in the design process the substrate noise injected by large digital circuits. Nowadays it is possible to build circuital substrate models, which along with the models produced by the traditional extraction tools for the active circuitry can produce a very accurate substrate aware model. Unfortunately t...