This paper proposes a novel adiabatic static random access memory (SRAM) using memristor. The proposed SRAM which is a sinusoidal driving consists of one NMOS transistor and one memristor (i.e. 1T1M type). The proposed SRAM also is driven by an optimal voltage resulting in a decrease of energy dissipation. From SPICE simulation results, we show that the energy dissipation of proposed 1T1M-SRAM ...

Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also ...

The short-term memory under consideration differs from other memory systems of the same sort in so far as it has the following properties: (a) storage of codes in the dynamic memory and analysis of codes are combined in time; (b) information is stored in both structures (dynamic and static) in a "squeezed" form and the degree of "squeezing" differs for dynamic and static memories: (c) codes may...

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Increasing dependence of the functionality and performance of computing system on the characteristics of the memory subsystem calls for further study on various memory technologies. Conventional memory technologies, such as SRAM, DRAM and FLASH, suffer from the formidable device scaling challenges, which makes researchers pay more attenti...

Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM

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0038-1101/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.sse.2010.06.009 * Corresponding author. E-mail addresses: [email protected] (R.W. Ma Wang), [email protected] (S. Nalam), sk4fs@virgin us.ibm.com (G. Braceras), [email protected] (H. Pilo) Calhoun). Large scale 6T SRAM beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations associated with scal...

This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data l...

In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose closed-loop ada...