Yield, Reliability and Power Supply considerations motivate the need to minimize power dissipation during test application. Two techniques for minimizing power dissipation when tests are applied to static CMOS combinational circuits are proposed. They are: (i) Test set ordering; and (ii) Repetition of test vectors. We show that: although (i) is NP-Hard good heuristics can be developed; and an o...

The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipation and the static power of the chip are increased. Power dissipation is one of the limiting factors in achieving the highest performance of a chip. Therefore, new power reduction techniques are required. In this paper a...

Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the ...

The viscoelastic effect of rubber material on creation of rolling resistance is responsible for 10-33% dissipation of supplied power at the tire/road interaction surface. So, evaluating this kind of loss is very essential in any analysis concerned with energy saving. The transient dynamic analysis for including the rolling effects of the tire requires long CPU time and the obtained results are ...

Leakage power is becoming the dominant power component in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM ...

In present scenario, an increasing demand for mobile electronic devices such as cellular phones, laptop computers and personal digital assistants requires the use of power efficient circuits. To minimize the power dissipation and to increase the battery lifetime, the supply voltage, VDD has been scaled down continuously. So, scaling down the supply voltage, without scaling down the threshold vo...

As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present a short-circuit power dissipation formula for static CMOS logic gates driving a CRC load. By representing the short-circuit current and the current flowing in the res...

Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also ...

This paper addresses power consumption in CMOS logic gates through an study considering the design and technology points-of-view. Through SPICE simulations, the relationship between charge/discharge and short-circuit components of dynamic power consumption are investigated both considering different logic gates and its evolution through technology scaling. Experimental results show that dynamic...

In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes mu...