This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.

In this paper, we propose a non-volatile SRAM, which presents simultaneously low power dissipation and high speed. This SRAM is based on MRAM (Magnetic RAM technology on standard CMOS. In this non-volatile SRAM design, we use Magnetic Tunnel Junctions (MTJ) as storage element. A 4-bit SRAM cell is designed and its read-write operations are described. Sense Amplifier is used in the read operatio...

Low threshold voltage and ultra thin oxide become essential in power optimal VLSI circuit design. This paper analyzes the effect of dual thickness and dual threshold on static random access memory (SRAM) leakage power. The different hybrid cell configurations are analyzed for power optimal design of SRAM in 90nm technology node. Cell ratio of SRAM is an essential parameter for area centric SRAM...

: In the microprocessors world SRAM play a vital role, but as the technology is scaling in nanometer, leakage current and leakage power both are the most known problems for SRAM cells in low power applications. More than 40% of the total power of the SRAM is waste due to the leakage through transistor. This paper compares the working, performance and results of two different SRAM topologies; a ...

ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the sta...

Scaling of gadgets in mass CMOS engineering helps short direct impacts and increment in spillage. Static arbitrary access memory (SRAM) is required to involve 90% of the zone of Soc. Since spillage turns into the essential variable in SRAM cell, it is actualized utilizing FinFet. FinFet gadgets got to be better option for profound submicron advances. In this paper, 6t SRAM cell is actualized ut...

This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data l...

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for ...

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much pr...