T In this paper, we propose an approach based on hardware-software partitioning to minimize logic area of a SOPC circuit "System on a Programmable Chip". This approach minimizes the SOPC area while satisfying a time constraint. To minimize this area, we propose an algorithm to determine the critical path with the largest number of hardware tasks in a given data flow graph. Once these hardware t...

Core Overview The data generation and monitoring solution for Avalon® Streaming (Avalon-ST) interfaces consists of two components: a data pattern generator core that generates data patterns and sends it out on an Avalon-ST interface, and a data pattern checker core that receives the same data and checks it for correctness. Both cores are SOPC Builder-ready and integrate easily into any SOPC Bui...

Real-world processes generally produce observable outputs, which can be characterized as signals. The signals can be discrete in nature (e.g., characters from a finite alphabet, quantized vectors from a codebook), or continuous in nature (e.g., speech samples, temperature measurements, music). The signal source can be stationary (i.e., its statistical properties do not vary with time), or non-s...

Accurate DNA segregation is essential for genome transmission. Segregation of the prototypical F plasmid requires the centromere-binding protein SopB, the NTPase SopA and the sopC centromere. SopB displays an intriguing range of DNA-binding properties essential for partition; it binds sopC to form a partition complex, which recruits SopA, and it also coats DNA to prevent non-specific SopA-DNA i...

It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP processor and FPGA. DSP processor offers high compute intensive complete embedded product where as FPGA offers high flexibility to a System on Programmable Chip (SoPC) designer for proof of concept at...

-----------------------------------------------------------Abstract----------------------------------------------------In many case on chip systems are used to reduce the development cycles. Mostly IP (Intellectual property) cores are used for system development. In this paper, the IP core is designed with ALTERA NIOSII soft-core processors as the core and Cyclone III FPGA series as the digital...

Description: A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist on memories, one or more microprocessors, interface devices, configurable logic blocs and other necessary components to achieve the intended function. In this work we aim to propose a new hardware-software partitioning algorithm of control data...

This paper presents a new True Random Number Generator (TRNG) based on an analog Phase-Locked Loop (PLL) implemented in a digital Altera Field Programmable Logic Device (FPLD). Starting with an analysis of the one available on chip source of randomness the PLL synthesized low jitter clock signal, a new simple and reliable method of true randomness extraction is proposed. Basic assumptions about...