The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and C.A synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under ...

Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is evaluated only if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of propositional logic (PL) that can be defined by short-circuit evaluation and implies the set of co...

One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrial-standard property-specification language called PSL. This development was enabled by the equally unlikely transformation of the mathematical machinery of automata on infinite words, introduced in the early 1960s for second-or...

In the history, the major issues of the VLSI designer were area, cost, performance, and reliability; power concern was typically of only lesser importance. But more than the last few years’ power in the circuit is the major difficulty at the present days which is being faced by the very large scale integration industries. The power dissipation in several circuits is typically take place by the ...

Methods for Reducing Events in Sequential Circuit Fault Simulation Elizabeth M. Rudnick Thomas M. Niermann Janak H. Patel Center for Reliable and Sunrise Test Systems Inc. Center for Reliable and High-Performance Computing Sunnyvale, CA 94086 High-Performance Computing University of Illinois University of Illinois Urbana, IL 61801 Urbana, IL 61801 Abstract Methods are investigated for reducing ...

Hardware verification and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verification it succeeds, if the implementation is correct with regard to its specification. This observation can be us...

In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF’s) and clustering the combinational part of the sequential circuit. This approach breaks ...