The IEEE 754 single precision floating point multiplier uses reversible exponent adder to accomplish multiplication operation. The REA is designed and implemented using reversible logic gates like Peres gate and TR gate. Reversible logic is used to reduce the power dissipation compared to classical logic and it can also reduces the information loss so which finds application in different fields...

International Technology Roadmap for Semiconductors (ITRS) set a road map for More than Moore (MtM). Where device is scaled more than what the moore’s law predicts. This MtM scaling will leads to substantially large design in the future and also huge power dissipation due to irreversible logic computation. Since applying low power technique has become tedious and time consuming. The solution is...

Multipliers play a vital role in digital systems especially in digital processors. There are many algorithms and designs were proposed in the earlier works, but still there is a need and a greater interest in designing a less complex, low power consuming, fastest multipliers. Reversible logic design became the promising technologies gaining greater interest due to less dissipation of heat and l...

Problem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-pro...

This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for 4:2 compressor optimised realisation using reversible logic. The proposed has ±1 Error Distance (ED) and 12.5% Rate (ER). efficacy of the logic based is measured in scales Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) Ancilla Input (AI). able to reduce metrics GC, QC, GO AI by 50%, 15%, 25%...

Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction an 8-, 16-, 32-, 64-bit multiplier using carry-save adder, Kogge stone and HNFG adder with high operating speed proposed gate adder. The architecture device logic gates which are reversible be implemented Vedic multiplier. outp...

Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. This paper proposes an improved design of a multiplier using reversible logic gates. Multipliers are very essential for the construction of various computational units of a quantum computer. The quantum cost of a reversible logic circui...