This work proposes and implements a reconfigurable parallel architecture based on dataflow for numerical computation, named PRADA. This architecture uses concepts of parallel processing to obtain a scalable performance and the dataflow concept for controlling the parallel execution of instructions. PRADA is composed by a control unit and several processing elements (PEs). In the control unit, t...

In this paper, we numerically simulated a glass-based all-optical 1×N power splitter with eleven different configurations using soliton breakup in a nonlinear medium. It is shown that in addition to reconfigurability of the proposed splitter, its power splitting ratio is tunable up to some extent values too. Nonlinear semivectorial iterative finite difference beam propagation method (IFD-...

In this paper; we introduce a coarse reconjigurable Multimedia Functional Unit (rMFU) extension to a superscalar General-purpose Processor (GPP) and a set of specialized multimedia instructions to extend the GPPs instruction set. Two multimedia operations, the DCT operation arid the HufJinan encoding operation, were chosen to assess the expected performance of our proposal. The performance of t...

This paper presents the implementation of an 8-point Inverse Discrete Cosine Transform (IDCT) computing resource on a TriMedia/CPU64 FPGA-based Reconfigurable Functional Unit (RFU). TriMedia/CPU64 is a 64-bit 5 issue-slot VLIW processor launching a long instruction every clock cycle. The RFU consists mainly of an FPGA core, and is embedded into the TriMedia as any other hardwired functional uni...

In this dissertation, we discuss the design of a reconfigurable, unified HMAC-hash unit for IPSec authentication. The proposed unit is reconfigurable at runtime to enable implementing any of six standard algorithms: MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1, and HMAC-RIPEMD-160. The designed unit can be used for IPSec or any other security application that uses hash functions, such as digita...

Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable processor involves a multitude of design decisions regarding the field-programmable structure as well as its system integration with the CPU core. Determining the impact of these design d...

Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common functional structures within Protein Interaction Networks. However, the increasing size of both the graphs to be searched and the target sub-graphs requires the use of large numbers of parallel conventional CPUs. This pa...

Due to the combination of flexibility and realization efficiency, reconfigurable hardware has become a promising implementation alternative. In the context of the IST-AMDREL project, a mixed granularity reconfigurable SoC platform targeting wireless communication systems has been developed. The platform’s main building blocks are presented, including coarse grain reconfigurable unit, embedded F...

Reconfigurable computing is a computer architecture which is intended to fill the gap between the hardware and the software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Most commonly and widely used high speed computing fabrics deployed in reconfigurable computing are field-programmable gate arrays (FPGAs). This pap...

Reconfigurable computing maps computation onto flexible and reprogrammable hardware. A typical reconfigurable computing (RC) system consists of a host processor (with a traditional architecture) and one or more reconfigurable coprocessors. Proposed hardware architectures for reconfigurable co-processors fall in two broad categories [4]: netlist computers with uniform arrays of fine grained logi...