We consider the problem of storing a string S in dynamic compressed form, while permitting operations directly on the compressed representation of S: access a substring of S; replace, insert or delete a symbol in S; count how many occurrences of a given symbol appear in any given prefix of S (called rank operation) and locate the position of the ith occurrence of a symbol inside S (called selec...

Network DRAM is the idea of using RAM on another workstation instead of local disk as a backing store for virtual memory. Network RAM generally has a lower access time than disk but has inferior fault tolerance. In this paper, we examine the benefit of network RAM when running some of the most popular LAPACK programs. We found that network RAM does not help these LAPACK programs as much as one ...

Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias wh...

Custom memory organization are challenging task in the area of VLSI design. This study aims to design high speed and low power consumption memory for embedded system. Synchronous SRAM has been proposed and analyzed using various simulators. Xilinx simulator simulates the Synchronous SRAM memories which can perform efficient read/write capability for embedded systems. Xinix tool also provide the...

To date all the proposals for low power designs of RAMs essentially focus on circuit level solutions. What we propose here is a novel architecture (high) level solution. Our methodology provides a systematic tradeoff between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance...

We examine the primary challenges for building a practical and competitive holographic random access memory (HRAM) system, specifically size, speed, and cost. We show that a fast HRAM system can be implemented with a compact architecture by incorporating conjugate readout, a smart-pixel array, and a linear array of laser diodes. It provides faster random access time than hard disk (100 microsec...

A reference generation scheme is proposed for a 1T-1C ferroelectric random-access memory (FeRAM) architecture that balances fatigue evenly between memory cells and reference cells. This is achieved by including a reference cell per row (instead of per column) of the memory array. The proposed scheme converts the bitline voltage to current and compares this current against a reference current us...

The ROBUST PRAM is a concurrent-read concurrent-write (CRCW) parallel random access machine in which any value might appear in a memory cell as a result of a write connict. This paper addresses the question of whether a PRAM with such a weak form of write connict resolution can compute functions faster than the concurrent-read exclusive-write (CREW) PRAM. We prove a lower bound on the time requ...