Although recursive filters are not possible to pipeline at the algorithmic level, it is possible to introduce logic level pipelining and thereby increase the maximal sample rate. This is because the critical path gets shorter so that the circuitry can be clocked faster. However, the latency of the operations increases with increased pipelining. It is of interest to find the optimal degree of pi...

Software pipelining is a loop optimization which can optimize loops better, even when all other techniques fail. In this project, Software pipelining is implemented using a scheduling algorithm called window scheduling in SimpleSUIF. Although the algorithm can not be applied to all loops, it is shown that for some loops the software pipelining can improve the performance significantly.

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challengi...

Wave-pipelining is a method of high-performance circuit design which implements pipelin-ing in logic without the use of intermediate latches or registers. This paper presents a tutorial of the principles of wave-pipelining and a survey of recent wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits. Wave-pipelining has recently drawn considerable inte...

Software pipelining is widely used as a compiler optimization technique to achieve high performance in machines that exploit instruction-level parallelism such as superscalar or VLIW processors. However, surprisingly, there have been few theoretical results on the optimality of software pipelined loops with control flows. The problem of time optimal software pipelining of loops with control flo...

When applications contain large loops, high level synthesis often takes advantage of software pipelining technique in order to improve the performance. High level synthesis with pipelining utilization needs complicated algorithms. So it is desired to check its correctness. In this paper, we propose a novel approach for equivalence checking of loops before and after pipelining. The proposed appr...

In parallelizing the code for high-performance processors, software pipelining of innermost loops is of fundamental importance. In order to beneet from software pipelining, two separate tasks need to be performed: (i) software pipelining proper ((nd the rate-optimal legal schedule), and (ii) register allocation (allocate registers to the found schedule). Software pipelining and register allocat...

Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try to reduce the prologue/epilogue produced by software pipelining. This paper presents the fundamental understanding of the relationship between code size expansion and software pipelining. Based on the retiming concept...