This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode “log-domain” oscillator in a classical PLL topology to obtain these features. The PLL has been fabric...

A novel frequency-to-voltage converter based phase-locked loop (PLL) is proposed to overcome the inability of a frequency-locked lock phase. The dual-loop PLL adds variable phase-locking capability, such that phase locking angle can vary from 0–360°. additional be applied in data communication form modulation. design targeted for 0.5-?m CMOS process. generates 480 MHz clock reference 15 MHz. In...

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-μm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and currentinjection current-mode logic (CICML) divider. A short-pulsed-reset phase fre...

This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3– 3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase det...

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discha...

We proposed a 24-GHz frequency synthesizer (FS) for automotive radar application, which consists of a phaselocked loop (PLL) and an injection-locked frequency multiplier (ILFM). Based on a novel topology, the multiply-by2 ILFM consists of a double-balanced mixer and an injectionlocked oscillator (ILO). The PLL is designed with a 12-GHz voltage-controlled oscillator (VCO) and an injection-locked...

The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the single phase utility interface inverters Phase-locked loops (PLL) are widely used in power electronics equipment connected to the mains. The use of a square wave voltage-controlled oscillator instead of a sinusoidal one eliminates one multiplier, resulting in a simple PLL algorithm, s...

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RM...

A phase-locked loop (PLL) angular modulator scheme has been proposed which has the characteristics of wideband modulation frequency response. The modulator design is independent of the PLL closed-loop transfer function H(s), thereby allowing independent optimization of the loop's parameters as well as the modulator's parameters. A phase modulator implementing the proposed scheme was built to ph...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...