The high performance of today's digital phase-lock loop makes it the preferred choice for generation of stablee low noisee tunable local oscillators in wireless communications applicationss This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase-Frequency Detector and a current switch charge pump such as National Semiconductor's PLLatinum TM Serie...

the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...

Directly detecting the phase of a baseband signal from the ratio of the in-phase and the quadrature phase component, a delta-sigma phase detector can realize an AGC-free mobile communication receiver. This paper studies the performance of the phase detector applied to digital communication systems. Theoretically explaining phase quantization noise of the detector, we show the performance of a P...

We have developed the effective algorithm for detecting digital binary phase-shift keyed signals. This algorithm requires a small number of arithmetic operations over the signal period. It can be relatively easy implemented based on the modern programmable logic devices. It also provides high interference immunity by identifying signal presence when signal-to-noise ratio is much less that its w...

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occup...

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are re...

In this paper we study and present some results on the performances of frequency tracking for Ka-band satellite communications in rain fading channels. The carrier frequency is tracked using a 2 order hyperbolic phase detector based digital-phase locked loop (D-PLL). The hyperbolic D-PLL has the capability of extending the tracking range compared to the other D-PLL and hence can be designed suc...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...