Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In the quest for rapid design turn-around, parallelization has been proposed to speed fault simulation. In this paper, we introduce ProperPROOFS, a parallel extension of the PROOFS fault simulation package. ProperPROOFS exploits parallelism based on fault partition...

We present a model for application-level fault tolerance for parallel applications. The objective is to achieve high reliability with minimal impact on the application. Our approach is based on a full replication of all parallel application components in a distributed wide-area environment in which each replica is independently scheduled in a different site. A system architecture for coordinati...

A new approach to parallel fault simulation for sequential circuits based on Binary Decision Diagrams (BDD) is proposed. The efficiency of BDDs for simulation is well known. However, traditional BDDs are not well-suited for fault simulation. Furthermore, up to now, they have not been used for parallel simulation. In the paper, a new class of BDDs is presented, called Structurally Synthesized BD...

This paper describes an approach to fault-tolerant parallel computing which is based on the experiences with the most successful fault-tolerant software – the transaction processing systems. The algorithms presented here have less runtime overhead and faster recovery than most preceding approaches. In the Pact parallel programming environment fault tolerance is provided fully user transparent i...

In this paper, fault-tolerant feature of TOPAS parallel programming environment for distributed systems is presented. TOPAS automatically analyzes data dependence among tasks and synchronizes data, which reduces the time needed for parallel program developments. TOPAS also provides supports for scheduling, load balancing and fault tolerance. The main topics of this paper is to present the solut...

Fault Detectors are valuable services which provide information about process failures in largescale parallel systems. Previous many studies suggest guidelines for the implementation of a fault detector. However, a practical approach to implementation is another challenge due to various parallel system environments of both hardware and software. This study explains that Fault detector is able t...

The protection of parallel transmission lines has been a challenging task due to mutual coupling between the adjacent circuits of the line. This paper presents a novel scheme for detection and classification of faults on parallel transmission lines. The proposed approach uses combination of wavelet transform and neural network, to solve the problem. While wavelet transform is a powerful mathema...

In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, an...