Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculusbased methodology is presente...

An efficient methodology for building the billiontransistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks will be required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that...

Integrated optical interconnect is believed to be one of the main technologies to replace electrical wires. Optical Network-on-Chip (ONoC) has attracted more attentions nowadays. Benes topology is a good choice for ONoC for its rearrangeable non-blocking character, multistage feature and easy scalability. Routing algorithm plays an important role in determining the performance of ONoC. But trad...

The packet switching based Network-on-Chip (NoC) is an obvious interconnect design alternative to the shared bus, crossbar or ring based on-chip communication architecture used in System-on-Chips (SoCs). The advent of the three dimensional NoC (3D NoC) architecture attracts added interest as it offers improved performance and shorter global interconnect. In the 3D NoC architecture, topology pla...

The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects....

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. However, the electronic network on chip design faces many problems like energy consumption, bandwidth and QoS. Compared with traditional electronic NoC, optical Network on Chip exhibits advantages of high-bandwidth, low latency and power dissipation. In this paper, a ...

The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects....

We propose 3D mesh-based optical network-onchip (ONoC) based on a novel low-cost 6x6 optical router, and quantitatively analyze thermal effects on the 3D ONoC. Evaluation results show that with the traditional thermal tuning technique using microheater, the average power efficiency of the 3D ONoC is about 2.7pJ/bit, while chip temperature varies spatially between 55C and 85C. In comparison, a n...

For the first time, the 4- and 5-port optical routers are designed by using the West First routing algorithm for use in optical network on chip. The use of the WF algorithm has made the designed routers to provide non-blocking routing in photonic network on chip. These routers not only are based on high speed Mach-Zehnder switches(Which have a higher bandwidth and more thermal tolerance than mi...

Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication....