Nanoscale I-MOS devices were demonstrated by using a novel device structure. They showed a normal transistor operation with subthreshold swing less than 12.2 mV/dec at room temperature. We also investigated some critical issues were also discussed in device design such as the junction depth of the source extension region and the substrate doping concentration.

A single electron memory was demonstrated in crystalline silicon that has a transistor channel width of ;10 nm and a nanoscale floating gate of dimension ;~7 nm 3 7 nm 3 2 nm!, patterned by electron beam lithography, lift-off, and reactive ion etching. Quantized shift in the threshold voltage and self-limited charging process have been observed at room temperature. Analysis has shown that these...

nano-crystalline Si dots of dimensions of 8nm have been incorporated into a variety of Coulomb blockade and floating gate memory devices. Structures include vertical transistor, planar electrode, nanoscale channel junction and 2-gate trench structure. Ballistic transport, Coulomb oscillation and memory effects are clearly demonstrated

The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s∗d tight-binding compu...

The development of strategies for addressing arrays of nanoscale devices is central to the implementation of integrated nanosystems such as biological sensor arrays and nanocomputers. We report a general approach for addressing based on molecular-level modification of crossed semiconductor nanowire field-effect transistor (cNW-FET) arrays, where selective chemical modification of cross points i...

Electrostatic counter ion screening is a phenomenon that is detrimental to the sensitivity of charge detection in electrolytic environments, such as in field-effect transistor-based biosensors. Using simple analytical arguments, we show that electrostatic screening is weaker in the vicinity of concave curved surfaces, and stronger in the vicinity of convex surfaces. We use this insight to show,...

Abstract—A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with...

In this paper, the electrical characteristics and sensitivity analysis of staggered type p-channel heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET) are thoroughly investigated via simulation study. The minimum lattice mismatch between InAs/GaAs0.1Sb0.9 layers besides low carrier effective mass of materials provides high probability ...

Thermal management has become a promising field in recent years due to the limitation of energy resources and global warming. An important topic improving efficiency thermal utilization is how control flows heat, rectifiers, such as transistor, have been proposed units for modulating flow heat. In this work, reconfigurable non-contact transistor with two-dimensional grating introduced. The cons...