This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation th...

for testing linked faults. We prove that new algorithms have higher fault coverage than existing march tests for linked multiple faults. Many fault models for RAMs and tests for faults of these models are available. In most cases these tests allow for the detection of single faults only. This paper contains fault coverage analysis of march tests which detect multiple faults. It is shown there a...

We compare the diagnostic accuracy of three diagnostic inference models: the simple Bayes model, the multimembership Bayes model, which is isomorphic to the parallel combination function in the certainty-factor model, and a model that incorporates the noisy OR-gate interaction. The comparison is done on 20 clinicopathological conference (CPC) cases from the American Journal of Medicine—challeng...

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We rst propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single or multiple path delay faults. Testing strategies for single primitive faults exist. In t...

Cell array faults in random-access memories (RAMs) are usually represented by Mealy automata. In such a model, multiple faults should also be representable by automata; in fact, it should be possible to compute the automaton representing a multiple fault from the automata representing the single faults that make up the multiple fault. In this paper we study properties of binary composition oper...

This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are denned. The failsafe design presented has limited fault-tolerance capability. Multiple faults are also covered.

A novel attitude tacking control method using Time Delay Control (TDC) scheme is developed to provide robust controllability of a rigid hexacopter in case of single or multiple rotor faults. When the TDC scheme is developed, the rotor faults such as the abrupt and/or incipient rotor faults are considered as model uncertainties. The kinematics, modeling of rigid dynamics of hexacopter, and desig...

This work proposes to put up a tool for diagnosing multi faults based on model using techniques of detection and localization inspired from the community of artificial intelligence and that of automatic. The diagnostic procedure to be integrated into the supervisory system must therefore be provided with explanatory features. Techniques based on causal reasoning are a pertinent approach for thi...

Single fault sequential change point problems have become important in modeling for various phenomena in large distributed systems, such as sensor networks. But such systems in many situations present multiple interacting faults. For example, individual sensors in a network may fail and detection is performed by comparing measurements between sensors, resulting in statistical dependency among f...

The aim of this paper is to investigate and detect the multiple faults in machines using broken rotor bar and eccentricity fault frequencies techniques. It is proposed that using both current and instantaneous power signals simultaneously, will detect the multiple faults reliably, specifically using broken rotor bar fault frequencies and eccentricity fault frequencies under various load conditi...