The end of Moore's law for CMOS technology has prompted the search low-power computing alternatives, resulting in promising approaches such as nanomagnetic logic. However, logic is unable to solve a class interesting problems efficiently, it only allows forward computing, due need clocking and/or thermal annealing. Here, we introduce self-organizing gates that can dynamically satisfy their logi...

XOR & AND gates are most important basic building blocks of any VLSI applications. These gates can be implemented in different architectures by using different circuit designs techniques. This paper evaluates and compares the performance of various design techniques of XOR-AND gates. The performances of these techniques have been evaluated by Tanner Tools V13 using the 90nm CMOS technology. In ...

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic...

This paper describes the architecture, design & simulation of ternary logic gates. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to devices [1]. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of ternary-valued logic circuits have been explored ov...

In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of individual electrons. More specifically, we focus on the implementation of a family of Boolean Single Electron Encoded Logic (SEEL) gates, in which the logic values 0 and 1 are encoded as a net charge of 0 or 1 electron charg...

We describe a high-speed physical random number generator based on a hybrid Boolean network with autonomous and clocked logic gates, realized on a reconfigurable chip. The autonomous logic gates are arranged in a bidirectional ring topology and generate broadband chaos. The clocked logic gates receive input from the autonomous logic gates so that random numbers are generated physically that pas...

Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive numbe...

Everything in the Universe is assumed to be compromised of pure reversible quantum Toffoli gates, including empty space itself. Empty space can be configured into photon or matter gates simply by swapping logic input information with these entities through the phenomenon of quantum mechanical entanglement between photons and empty space Toffoli gates. The essential difference between empty spac...