Effects of a lightly-doped-drain (LDD) implantation condition on the device characteristics of poly-Si TFT have been studied. For a LDD implantation dose of 2–4 × 1013 cm−2, no significantly large difference in on-state current and off-state leakage is found. For a LDD implantation energy of 50–100 keV, however, the higher LDD implantation energy results in smaller off-state leakage and more re...

In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thinfilm transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs wi...

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Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including sub...

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Ion implantation of dopant impurities to form p-n junctions and other doped regions in silicon transistors has evolved from an experimental curiosity in solid-state physics to become a dominant technology in today’s integrated circuit manufacturing. This paper traces the key inventions and early developments in ion beam doping concepts from the early 1950’s through the 1970’s as they were appli...

In this article, the particle irradiation effect of a lightly doped Gaussian source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET) is discussed. phenomenon, heavy ion produces series electron-hole pairs along incident track, and then generated transient current can overturn logical state device when number large enough. single-particle DMG-GDS-HJLTFET, carried ene...

Noise Coupling in Heavily and Lightly Doped Substrate from Planar Spiral Inductor Tony Yeung, Alan Pun, Zhiheng Chen, Jack Lau, Fran cois J.R. Cl ement Dept. of Electrical & Electronic Engineering, The Hong Kong University of Science & Technology Center for Integrated Systems, Stanford University, Stanford, CA 94305 Abstract| Recently, much studies have been done to include on-chip inductors fo...

This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension a...

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by dividing into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance considering the nonnegligible doping-depend...