In this paper, an efficient algorithm to design convolved LFSR/SR (Linear Feedback Shift Register / Shift Register) for the pseudo-exhaustive testing (PET) is presented as far as the lengths of the test set and hardware overhead are concerning. In this algorithm, an efficient search to reduce the constraint in the size of the shift register (SR) segment and makes an efficient search to restrict...

In circuit theory, it is well known that a linear feedback shift register (LFSR) circuit generates pseudorandom bit sequences (PRBS), including an M-sequence with the maximum period of length. In this study, we tried to detect M-sequences known as a pseudorandom sequence generated by the LFSR circuit from time series patterns of stimulated action potentials. Stimulated action potentials were re...

This paper presents a developed tool for PseudoRandom Binary Code generator (PRBCG). Based on extensive study of LFSR theory we developed the simulation model of PRBCG. The developed model is faster and simulates the process for very high length of Linear Feedback Shift Registers (LFSRs). We tested our model for the value n = 300 where n is the length of the LFSR. The developed software model i...

In high-performance processors, the accuracy of branch prediction plays a significant role in enhancing computer execution. A new hardware approach is presented in this paper to dynamically predict branch directions using path information. As an execution path contains large information, we compress the large information using a technique based on the linear feedback shift register (LFSR) that ...

Abstact A new design approach is proposed for a fault coverage circuit. In this design a linear feedback shift register which is called as LT_LFSR (Low Transition Linear Feedback Shift Register) is used. Using LT_LFSR reduces the power consumption by reducing the number of transitions during test mode. Power reduction is done by implementing two new test pattern generation methods in LFSR. In b...

An analysis of the Berlekamp-Massey Linear Feedback Shift-Register (LFSR) Synthesis Algorithm is provided which shows that an input string of length 12 requires C ( i 2 ) multiplication/ addition operations in the underlying field of definition. We also derive the length distribution for digit strings of length n. Results show that, on the average, the encoded length is no greater than n + l . ...

Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudo-random binary sequences from such structures. Keywords—LFSR, external exclusive NOR type, recursive binary sequence, initial state next state, state transition matrix.

In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The seeds are obtained by solving systems of l...

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. If the clock frequency which is slo...

VLSI circuit’s encounters are rapidly many challenging tasks of semiconductor manufacturing along operating with gigahertz range of frequencies. These challenges are include keeping peak power dissipation and the application time within limits. In this Paper we are proposes a new approach of low power Test Pattern Generator (TPG) designed by modifying parallel Linear Feedback Shift Register (Pa...