نتایج جستجو برای: jitter transfer and jitter tolerance

تعداد نتایج: 16895586  

2009
Omer Gokalp Memis Alex Katsnelson Hooman Mohseni Minjun Yan Shuang Zhang Tim Hossain Ilesanmi Adesida

The transient response of a nanoinjection infrared photon detector was studied by exploring the relation between lateral charge transfer and jitter. The jitter of the device was measured to be 15 ps at room temperature. The jitter was almost independent of the pulse power, even after device saturation. Spatial maps for delay and amplitude were acquired. The carrier velocity was extracted from t...

2010
Yang Jiang Kim-Fai Wong Chen-Yan Cai Sai-Weng Sin Seng-Pan U Rui Paulo Martins

A clock generation technique for reducing the clockjitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digit...

1997
Roger Taylor

This application note presents guidelines for measuring whether a design is compliant with AT&T 62411 jitter tolerance, jitter generation and jitter attenuation requirements. 62411 compliance is a necessary requirement for CPE (Customer Premises Equipment) which is connected to T1 lines provided by AT&T. These T1 lines may be either private-line or centraloffice access lines. 62411 may not appl...

2001
M.-J. Edward Lee William J. Dally Ramin Farjad-Rad Ramesh Senthinathan

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

2009
Minchul Shin Changwook Yoon Jeonghyeon Cho Jongjoo Shim Yujeong Shim Joungho Kim

In this paper, we analyze a noise-to-jitter transfer function on DLL (Delay Locked Loop) considering power supply noise effects on PDN (Power Distribution Network). Noise-tojitter transfer function of DLL circuit can be estimated by using single-tone power supply noise analysis. Noise transfer function through the PDN can be obtained from transfer impedance of hierarchical PDN using TLM (Transm...

2002
Hanjun Jiang Chengming He Degang Chen Randall Geiger

An optimal loop parameter design method of charge pump PLLs for jitter transfer characteristic optimization is proposed. Based on the linear model of charge pump PLLs, the relationship between PLLs’ loop parameters and jitter transfer characteristic is illustrated. Using the proposed optimal design method, a design example is done and the expected simulation result is obtained.

M Dehghan M.S Sif panahi T Salmalian

Background & Aims: Previous studies have indicated significant differences in vocal parameters between children with Down syndrome and normal children, but there are challenges about these differences. In this study vocal parameters and Maximum Phonation Time (MPT) in adults with Down syndrome have been investigated. Method: This cross-sectional and analytic study was performed on 22 adults wit...

2010
Meera Srinivasan Andre Tkacenko Mark Lyubarev Polly Estabrook

In this article we characterize the effect of transmitter clock jitter upon receiver symbol synchronization performance. Using a sinusoidal model for the timing jitter, we evaluate the bit error rate (BER) degradation and cycle slip probabilities of receivers via analysis as well as simulation for uncoded offset quadrature-phase-shift-keying (OQPSK). We evaluate performance for two different sy...

2013

The paper is organized as follows. The definition of jitter transfer and its relevance to high-speed standards is first presented. We then describe the measurement concept used in this paper and construct a very simple Introspect ESP Test Procedure for the automatic collection of PLL jitter transfer functions and loop bandwidth parameters. We then describe advanced topics related to min-max VCO...

ابریشمی فر, سید ادیب , معاضدی, مریم ,

Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. Supporting the highest bandwidth data rates among devices requires advanced clock management technology such as delay-locked loops (DLLs). The DLL circuitry allows for very precise synchronization of external and internal clocks. In this paper a low jitter and...

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